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Knowledge of component packaging

Because the electronic components must be isolated from the outside world to prevent the impurities in the air from corroding the chip circuits, resulting in a decline in electrical performance.On the other hand, packaged chips are also easier to install and transport.Because packaging technology also directly affects the performance of the chip itself and the design and manufacture of the PCB(printed PCB) connected to it, it is of vital importance.

The important index to measure the advanced packaging technology of a component is the ratio of chip area to package area, the closer the ratio is to 1, the better.Main considerations in packaging:

1. The ratio of chip area to packaging area is to improve packaging efficiency, which is close to 1:1.

2. The pins should be as short as possible to reduce delay, and the distance between the pins should be as far as possible to ensure non-interference and improve performance;

3. Based on the requirement of heat dissipation, the thinner the package, the better.

component packaging

There are two main types of encapsulation: DIP bilinear interpolation and SMD patch encapsulation.From the aspects of structure, encapsulation has experienced the most early TO the transistor (e.g., the TO – 89, TO92) development in the dual in packaging, then developed by PHILIP company SOP small appearance packaging, gradually derived SOJ small outline package (J type pin), TSOP (thin small outline package), VSOP (very small outline package) and SSOP (SOP) narrow type, TSSOP type (thin narrow SOP) and SOT (small outline transistor), SOIC (small outline IC), etc.In terms of materials and media, including metals, ceramics, plastics and plastics, there are still a lot of metal packaging for circuits with high strength working conditions such as aerospace level.

Encapsulation has roughly gone through the following development process:

Structure: TO->DIP-> plcc-> qfp-> bga-> CSP;

Materials: metal, ceramics -> ceramics, plastics -> plastics;

Pin shape: long straight pin inserted -> short lead or no lead attached -> spherical convex point;

Assembly method: through hole mounting -> surface mounting -> direct mounting

The specific form of encapsulation

1. SOP/SOIC package

SOP is short for Small Outline Package, that is, Small Outline Package.SOP packaging technology was successfully developed by philips from 1968 to 1969, and gradually derived SOJ (J pin small shape packaging), TSOP (thin small shape packaging), VSOP (very small shape packaging), SSOP (reduced size SOP), TSSOP (thin reduced size SOP), SOT (small shape transistor), SOIC (small shape integrated circuit), etc.

2. DIP packaging

The DIP is an abbreviation of the Double in-line Package, which is a double-in-line Package.One of the package types, pins from both sides of the package, packaging materials are plastic and ceramic.DIP is the most popular plug-in package, including standard logic IC, memory LSI, microcomputer circuits and so on.

3. PLCC packaging

The abbreviation of PLCC is English Plastic Leaded Chip Carrier, namely the encapsulation J lead Chip encapsulation.PLCC package, the shape is square, 32 – pin package, surrounded by pin, the size of the shape is much smaller than the DIP package.PLCC package is suitable to install wiring on PCB with SMT surface mounting technology, which has the advantages of small size and high reliability.

4. TQFP packaging

TQFP is short for the thin quad flat package, which is a thin molding seal with four corners flat package.The four-sided flat package (TQFP) process can effectively use the space, thus reducing the requirement of PCB space size.Due to its reduced height and volume, this packaging process is well suited for space-demanding applications such as PCMCIA CARDS and networking devices.Almost all CPLD/FPGA of ALTERA have TQFP encapsulation.

5. PQFP packaging

PQFP is an abbreviation of Plastic Quad Flat Package, which is a Flat Package with four corners.PQFP encapsulates chip pins with little distance between them and very thin pin. Generally, large or very large scale integrated circuits adopt this type of packaging, and the number of pins is generally more than 100.

6. TSOP packaging

TSOP is short for Thin Small Outline Package, which is a Thin Small size Package.A typical feature of TSOP memory encapsulation technology is to make pins around the encapsulated chip. TSOP is suitable for the installation of wiring on PCB (printed PCB) by SMT technology (surface mounting technology).The parasitic parameters (output voltage disturbance caused by the large change of current) are reduced when the TSOP package is in the external dimension. It is suitable for high frequency application, easy to operate and high reliability.

7. BGA packaging

BGA is an abbreviation of Ball Grid Array Package, namely Ball Grid Array Package.In the 1990s, with the progress of technology, the degree of chip integration was continuously improved, the number of I/O pins increased sharply, the power consumption was also increased, and the requirement of integrated circuit packaging was also stricter.To meet the needs of development, BGA packaging began to be applied in production.

component packaging

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